1. Field of the Invention.
The present invention relates to a semiconductor device whose resistance is varied from a high resistance value to a low resistance value irreversibly by applying an electric field and, more particularly, to a semiconductor device having electrically programmable read-only memories.
2. Prior Art.
A so-called antifuse device having amorphous silicon layers inserted between successive electrodes has been used as a semiconductor device whose resistance is varied from a high value to a low value irreversibly by applying an electric field. Especially, where antifuse devices are used in an electrically programmable read-only memory, it has been the common practice to add a diode to each individual storage element thereby making the ROM circuit configuration simpler. Such a diode is created by forming a Schottky junction layer on a lightly doped N-type semiconductor layer, the junction layer including platinum.
A known semiconductor device is shown in FIG. 2, where a diffused layer formed in a silicon substrate is used as one electrode of a storage element. The silicon substrate, indicated by 201, is of the P type. Created over the substrate 201 are a selectively oxidized film 202 forming a field-insulated, or device isolating, film, an N.sup.+ -type diffused layer 203, an interlayer insulating film 204, an N.sup.- -type diffused layer 205, a platinum silicide layer 206, an amorphous silicon film 207, and a conductive film 208 for forming metal interconnections. The insulating film 204 is made from silicon oxide, for example.
In this device, the N.sup.- -type diffused layer 205 is in contact with the N.sup.+ -type diffused layer 203. The platinum silicide layer 206, the amorphous silicon film 207, and the film 208 for forming metal interconnections are laminated on the diffused layer 205 which serves as a lower electrode. The film 208 acts as an upper electrode. In operation, an electric field is applied between the upper and lower electrodes to cause avalanche breakdown in the amorphous silicon film 207. At this time, Joule heat is evolved to change parts of the amorphous silicon film 207, thus forming low-resistance regions. The rectifying function of the Schottky diode between the platinum silicide layer 206 and the N.sup.- -type diffused layer 205 is combined with the low-resistance regions of the amorphous silicon film 207 to provide the known, electrically programmable read-only memory.
Another known semiconductor device is disclosed in U.S. Pat. No. 4,442,507. This device has a polycrystalline silicon layer which is formed on a silicon substrate and acts as one electrode of each storage element. In particular, the polycrystalline silicon layer is heavily doped so as to exhibit N-type conductivity. Another polycrystalline silicon layer formed on the heavily doped silicon layer is lightly doped and of the N-type conductivity. A platinum silicide layer, an amorphous silicon film, and a film for forming metal interconnections are deposited on the lightly doped polycrystalline silicon layer. The film forming the metal interconnections forms upper electrodes. Schottky diodes that are created between the platinum silicide layer and the lightly doped N-type polycrystalline silicon layer are employed.
In this known device, the lightly doped N-type diffused layer is formed to create the Schottky junctions. This presents the following problems.
(1) The resistance obtained after programming the device increases by an amount equal to the resistance of the lightly doped N-type diffused layer (examples 1 and 2).
(2) Where programmable elements are formed in series on the same lower electrode, the resistance of the lower electrode further increases by an amount equal to the resistance of the lightly doped N-type diffused layer (example 1).
(3) The resistance of the thin N-type diffused layer is easily modulated with voltage and so the resistance values of the programmed device easily vary during operation (example 1).
(4) When the thin N-type diffused layer is formed to create the Schottky junctions, it is necessary to take account of allowance for alignment. This increases the area of patterning (example 1).